On the design challenges of drain extended FinFETs for advance SoC integration

In this paper, for the first time, challenges associated with high voltage drain extended device design in nanoscale FinFET technology is discussed in context of System on Chip (SoC) integration. Using 3D technology CAD, performance figures of merit matrix for integrated switching applications, quasi saturation, device scaling, ESD reliability, self-heating behavior and Safe Operating Area (SOA) concerns are comprehensively correlated/compared with planar drain extended MOS device.