Analysis of neutron-induced soft error rates on 28nm FD-SOI and 22nm FinFET latches by the PHITS-TCAD simulation system

FinFET and FD-SOI processes reduce radiation- induced temporal errors and improve circuit reliability without any performance overhead. We calculate neutron-induced SEU (Single Event Upset) rates on 28nm FD-SOI and 22nm FinFET Flip-Flops by using TCAD and PHITS in order to compare SEU rates in advanced planar and 3D transistor processes. Simulation results show that SEU rate on 22nm FinFET is about 1/10 that on 28nm FD-SOI.