Modeling electromigration in nanoscaled copper interconnects

In this work we present an approach to modeling grain boundaries and material interfaces in nanoscaled copper interconnects. Using a sample structure with a 40nm×40nm cross section and an applied current density of 1MA/cm
²
, we perform a comparative analysis while ignoring or including grains, with an average grain size of 50nm. The novelty in our approach is the treatment of microstructure interfaces using a binary parameter, which is further used to define interface-specific material properties for copper resistivity and electromigration modeling. Our models show that the inclusion of microstructure effects results in an increased resistance, increased vacancy migration, and ultimately in a higher EM-induced stress.