A SPICE-compatible model of SG-MONOS for 28nm flash macro design considering the parasitic resistance caused by trapped charges

A SPICE-compatible model for the read current of split-gate MONOS (SG-MONOS) cell has been developed for 28nm embedded flash macro design. The influence of trapped charges on the read current has been analyzed by using TCAD. It has been found that trapped charges located on top of the gap region strongly decrease the cell current. It has been also found that the shape of I
d
-V
sg
curve changes drastically depending on the positon of trapped charge and trap density. This paper proposes a new model which reproduces the above behavior by using a synthesis of several resistances in which every resistance changes its value exponentially to the gate voltage. The model shows an excellent fitting accuracy for 28nm generation cell.