Optimal Register Alignment of Data Processing in Mesochronous Scheme

This paper present an optimal register alignment for minimization of clock switching scheme in Mesochronous operation. In Mesochronous operation, data are processed in one or more processing clocks based on executing instructions. In this scheme, a delayed clock pulse is allotted for each instruction in the processing unit. Due to different clock frequencies for different instructions, the overhead of clock allocation is large. The conventional models derive the clock delay per cycle, building a large overhead in Mesochronous operation. This overhead is reduced, by a register alignment logic, where the redundancy of instructions are realigned in a clock Look Up Table (LUT), and an instruction index alignment is proposed to minimize the switching overhead of clock allocation for Mesochronous operation. The simulation results obtained illustrates the efficiency in clock saving in comparison to conventional clock allocation logic.