High speed system level PDN analysis: Developing FPGA VCCR PDN specification to avoid transmitter phase noise

This paper is focused on high speed transceivers system level PDN modeling and analysis to avoid transmitter phase noise. Transmitter phases noise impacts output jitters and eventually falls into failing category for some high-speed protocols. A system level PDN specification is developed based on a good reference board design and all other customers and development kits are evaluated based on reference design.