Reconfigurable FIR filter for denoising of ECG signal

This paper presents a FIR Equiripple low pass filter design based on FPGA for eliminating high frequency noise from ECG signal. The filter architecture is partly serial and it is designed in MATLAB using direct form symmetric structure because implementation cost of symmetric structure is low as compared to direct form. The filter is designed using 16 bit input output precision. The filter design is synthesized on 2vp30fg676 and 5vlx50tff1136 device. Verilog Hardware Description Language (VHDL) is used for implementation of filter design on FPGA. Since coefficients are quantized in MATLAB to reduce design area and Xilinx 10.1 is used to simulate and synthesis the filter. Device utilization summary and speed comparison shows that filter design based on Virtex 5 is most speed efficient and device utilization ratio of partly serial architecture is better than fully parallel architecture.