An ADPLL-Based PSK Receiver for VHBR 13.56-MHz Contactless Smartcards and NFC Applications

This brief proposes an all-digital phase-locked loop (ADPLL) used as the phase-shift keying (PSK) receiver for a very high bit rate of 13.56-MHz smartcards. A detailed implementation from system to circuit level is presented. This ADPLL-based PSK demodulator mainly consists of a high dynamic range time to digital converter (TDC) without pulse shrinking effect, a dual-path digital loop filter, and a fine resolution digital controlled oscillator based on capacitor division without dithering. This design is fabricated by GF CMOS 40-nm technology with a core area of only 0.035 mm
²
. The measurement results show low current consumption of 40 mA for phase locking and 70 mA for PSK demodulation with 1.2-V supply. Both integral non-linearity and differential non-linearity of our TDC are smaller than 0.6 LSB. This prototype can demodulate 8-PSK at a symbol rate of 6.78 MHz, corresponding to a data rate of 20.34 Mb/s, with an energy efficiency of 4.1 pJ/bit.