A low power vernier Time-To-Digital converter using adiabatic logic

In this paper, an adiabatic based vernier time-to-digital converter (VTDC) is proposed. Generally, static based vernier TDC consumes more power due to two delay chain and D-flipflop. To avoid this issue an adiabatic based vernier TDC is proposed. This proposed TDC is constructed by using adiabatic inverter and D-flipflop but in classical TDC architecture consists of static based inverter and D-flipflop. A high resolution with low power is achieved in proposed TDC. Here, 2 stages, 3 stages, 4 stages traditional and proposed vernier TDC are implemented and also discussed about power consumption comparison of 2 stages, 3 stages, 4 stages conventional and proposed vernier TDC at different supply voltages. This vernier TDC is simulated in 180nm CMOS technology. Its operating frequency is 1.5KHZ.