Multilevel inverter with reduced number of switches

Multilevel inverters have been deliberated for an increasing number of application due to their high power capability. This paper discusses about a multilevel inverter topology with reduced number of switches, where sinusoidal pulse width modulation (SPWM) is used to produce a seven level output voltage. Also an L-C Filter is used at the output of the inverter to suppress the ripples in the output and produce the pure sinusoidal output voltage. Harmonics and switching losses can be reduced by this topology. And reduction of switches also reduces the cost. Multilevel inverters are used in industry for medium and high voltage application. The main disadvantage of this multilevel inverter is that it require complex gate driving circuit.