A leakage-tolerant 16-bit diode footed domino comparator using lector technique

The continuous scaling has resulted in increased sub-threshold leakage current due to decreased threshold voltage. LECTOR is a technique to reduce the problem of leakage in CMOS circuits, it includes a n-type and p-type leakage controlled transistors (LCTs), between supply to ground which are self-controlled and offers the extra resistance, which will reduce the problem of leakage current in the CMOS circuits. In this paper 16-bit Lector based diode footed domino (DFD) comparator is introduced, which provides 64% efficient reduction in leakage and is efficient in terms of performance compared to 16-bit DFD comparator. Simulations are performed in gpdk_90 nm CMOS technology using cadence virtuoso tool.