An efficient VLSI architecture for a serial divider

Processors play a very crucial role in every digital systems. The major blocks include the arithmetic logic units where arithmetic divider modules are frequently required for digital signal and image processing applications. SOC designers have to focus on the design of these dividers to increase the performance, accuracy and functionality of the processors. The division operation completes after several clock cycles which is more as compared to other modules in the arithmetic logic unit. This paper describes the architecture of an arithmetic serial divider. The divider circuit is designed using an adder/subtractor cell and non-restoring algorithm is used to the evaluate the result. CADENCE 90nm technology library is used for designing the architecture of the divider module.