Design of low power 12-bit magnitude comparator

In the advanced technology low power, speed and size play a significant role specifically in the field of magnitude VLSI circuits. In this paper small power dissipation and less area over conventional 2-bit comparator is proposed and using this comparator a new style 12-bit comparator is proposed. The main objective of this paper is to design and implement of magnitude comparator using different logic techniques and compared in terms of power consumption, propagation delay and transistor count. The results of this paper are simulated on the EDA tanner tool realized in 45-nanometer technology at 0.7v supply voltage.