An area-efficient 0.25 /spl mu/m memory compiler designed for 780 MHz operations

Embedded memories are indispensable components in today's system-on-chips. High-speed memories are highly valued by the ASIC designers. Designing a flexible, yet high speed (780 MHz), SRAM compiler faces many challenges. We have managed to develop such a memory compiler without penalizing area and power. Moreover, we extended our compiler to support the common design views needed in typical ASIC design flow. In this paper, we describe some of the critical issues and techniques in the development of a high-speed memory compiler.