CMOS ESD protection circuits utilizing submicron transistors operating in the snapback mode

The advancement of CMOS IC technologies presents increasing challenges in the design of reliable electrostatic discharge (ESD) protection. This paper presents novel CMOS ESD protection circuits using submicron MOS devices in the snapback region of operation. The measured characteristics of these ESD circuits are compared to simulations in HSPICE using previously developed models of MOS transistors in snapback.