Real-time track reconstruction during readout using an artificial retina architecture

We present the results of a study of the feasibility of implementing real-time track reconstruction within the framework of a pre-existing readout system, using the “Artificial Retina” approach. This is the first attempt at building a complete medium-size prototype of this kind (comprising about 8M Logic Elements, distributed on several separate boards), operating it continuously at its limit speed. This study emphasizes logic architecture, correct operation, size, and compatibility with a standard readout framework, to explore its useability as an add-on to a conventional readout system. For this reason we have chosen for implementation a moderate-cost, moderate-speed board already in use in the data acquisition of an existing HEP experiment. Our choice fell on the readout boards currently in use by the NA62 experiment (TEL62), each equipped with 5 Altera Stratix III FPGAs and 4 Gbit/s ethernet interface. We have reprogrammed the board firmware in two different ways, to make the boards behave as the two main blocks of a AR system (switch system, and cellular processor farm). They are interfaced via the front panel, inverting their normal data flow path, by custom interconnection boards, and developed in internal sytem for continuous feeding of data in order to test them at their maximum achievable speed. We report the results of extensive tests performed with this prototype, and discuss their implications regarding the applicability of the “retina architecture” to faster, and custom-developed real-time processors.