Geiger-mode avalanche pixels in 180 nm HV CMOS process for a dual-layer particle detector

The main purpose of this work is to investigate the characteristics of a 180nm CMOS technology with high voltage (HV) option in view of the fabrication of a dual-tier, low material budget sensor for charged particle detection. For this purpose, an array of avalanche pixels has been designed. The array includes sensors with a pitch of 50μmx100μm, different sizes (20μmx20μm, 30μmx30μm and 40μmx36μm) and different process layers. Active and passive quenching techniques to suppress the avalanche have been implemented in the front-end electronics, which is integrated in the same substrate as the sensor. The paper presents the results from the characterization of the test chip in terms of breakdown voltage and dark count rate (DCR).