Single-chain 4-channels high-resolution multi-hit TDC in FPGA

We present a TDC architecture designed for being implemented in a FPGA device with the highest regard to the trade-off among resource saving, resolution and input rate. In particular, 4 channels with a single physical measurement line guarantee resolution below 32 ps r.m.s. per channel at the input rate of events equal to 2 GHz. The system is composed of a single tapped-delay-line of length equal to the clock period where the 4 input channels merge, a register of the occurring events, and just one coarse counter.