Experimental investigation and physical explanation of shallow trench isolation stress effect in MOSFETs

STI has a significant impact on the channel carrier mobility in MOSFETs on account of the stress it introduces. This paper discusses the use of constant energy valleys of conduction and valence bands to explain CMOS Shallow Trench Isolation (STI) stress effect. The effect is observed to be dependent on channel's crystallographic orientation. By determining the current flow direction and the STI stress direction on the energy valleys, the CMOS drain current degradation or enhancement due to the mechanical stress effect can be identified. The amount of current degradation is about 2.5% in case of NMOS and is enhanced by 2.5% in case of PMOS for nominal sizes. The silicon data from 0.18μm CMOS technology supports the hypothesis in this paper.