Silicon based MM wave IC design for 60 GHz and beyond

This paper briefly presents a 60-GHz dual-chip wireless communication solution adhering to the IEEE 802.11ad standards. The proposed fully-integrated transceiver front-end chip (RFIC) using a sub-harmonic sliding-IF scheme to reduce the design difficulty on VCO, was implemented based on a low cost SiGe 0.18um BiCMOS process and has a compact chip area of 5mm by 3.9mm with a low power consumption of 218mW for TX mode and 261mW for Rx mode. The baseband IC (BBIC) uses adaptive time domain equalizer to perform synchronization, automatic gain control and to lower the chip size and power consumption.