Implementation of a novel cache memory unit for storing processed data and instructions

A cache memory unit and controller that makes instructions requiring large number of clocks by the processor more efficient. This cache memory has been introduced as an intermediary memory unit between the L1 cache and the processor. This specialized memory stores the instruction and the related data requiring large number of clock cycles for execution. Accordingly, a control unit and a cache memory has been designed. Instructions requiring less number of clock cycles for execution by processor than the number of clock cycles required for fetching it from the cache memory are not stored in the memory unit.