Understanding of slow traps generation in plasma oxidation GeOx/Ge MOS interfaces with ALD high-k layers

A small amount of slow trap density in Ge gate stacks is a crucial issue for Ge CMOS, in addition to thin equivalent oxide thickness and low interface state density. In this paper, we study the slow trap position and the generation mechanism in the high-k/GeO
_x
/Ge interfaces fabricated by plasma oxidation. The slow trap density in Al
₂
O
₃
/GeO
_x
/Ge interfaces by plasma pre-oxidation is compared with different GeO
_x
and Al
₂
O
₃
thickness, and the interfaces by plasma post oxidation (PPO). ALD Al
₂
O
₃
, HfO
₂
, La
₂
O
₃
and Y
₂
yO
₃
/GeO
_x
/Ge MOS interfaces are compare in terms of the slow trap density. It is found the main slow traps in Al
₂
O
₃
/GeO
_x
/Ge can locate near the GeO
_x
/Ge interfaces for electrons and the Al
₂
O
₃
/GeO
_x
interface for holes. It is also found that additional slow traps near conduction band side are generated during the PPO process. It is revealed that slow traps are generated by post high-k ALD, while Al
₂
O
₃
provides the lowest slow trap density in comparison with Y
₂
O
₃
, HfO
₂
and La
₂
O
₃
high-k films.