Physical modeling of the hysteresis in M0S2 transistors

The hysteresis in the gate transfer characteristics of transistors made of two-dimensional materials is one of the most obvious problems of this novel technology. Here we attempt for the first time to develop a physical modeling approach for describing this hysteresis in devices based on two-dimensional materials. Our model is based on a drift-diffusion TCAD simulation coupled to a previously established non-radiative multiphonon model for describing charge capture and emission events in the surrounding dielectrics, which are considered the main cause for the observed hysteresis. We validate our model against measurement data on a back-gated single-layer MoS
₂
transistor with SiO
₂
as a gate dielectric. Our study provides new insights into the physical reasons for the observed hysteresis, thereby leading the way towards an alleviation of this problem in future devices.