CubicWare: a hierarchical design system for deep submicron ASIC

In this paper, we present CubicWare, a hierarchical design system which can estimate both timing and power consumption at the pre-layout stage. CubicWare consists of a floorplanner (CubicPlan), a delay calculator (CubicDelay), and a power estimator (CubicPower). CubicPlan provides accurate estimation of the interconnect parasitics, and CubicDelay calculates the delay including the effect of interconnects. Based on this delay, logic simulation is performed to verify the functionality and timing of the design. In the process, switching statistics on each gate is obtained. CubicPower reads the switching statistics and the power characteristics of gates to estimate the power consumption. The proposed parasitics estimation algorithm in CubicPlan can consider the coupling capacitances of the interconnects using the wiring congestion map. This approach provides a significantly improved correlation with the post-layout than the conventional statistical methods in terms of interconnect capacitances. CubicWare also supports the full functions of hierarchical manipulations including hierarchical delay calculation. The timing estimation of CubicWare at the pre-layout stage shows less than 10% error compared to the post-layout result. Experimental results of the dynamic power estimator at the gate level shows less than 10% error compared to the results of Powermill and the measured values of the IMS tester.