An educational FPGA design process flow using Xilinx ISE 13.3 project navigator for students

Most Verilog and VHDL design processes, reported in current publications, lack detailed information on the procedures required to design on the Field Programmable Gate Array (FPGA) platform. Current reports do not provide a systematic and standard design process for students in Verilog and VHDL programming from the distinct aspect of teaching and learning point of view. In this work, a comprehensive design flow has been proposed to give an effective yet simple guideline in the assembly of Field Programmable Gate Array design using Verilog and VHDL programming language, either with or without employing Xilinx IP. A 16-bit shift register design had been demonstrated to verify the method proposed. System performance criteria specifically the number of flip-flops used; and fan-out of non-clock nets, were evaluated. This work has been conducted with an assessment using statistical analysis. It is observed that the experiment is more effective when conducted in a group. A complete design flow which consists of sufficient procedures needs to be developed as guidelines for students. It is required for students to have basic knowledge on programming language before they start programming using Verilog or VHDL. Based on observation, it is crucial to have proper procedures to guide students at the beginning of the experiment which prepares them for open-ended experiment later.