An effective and efficient algorithm to analyse and debug clock propagation issues

The evolution of deep submicron (DSM) era has resulted in rapid shrinking of the System-on-Chip (SoC) simultaneously with the exponential increase in the design complexity. Larger designs require numerous Intellectual Properties (IPs) composed of millions of combinational and sequential cells to serve the purpose which further require an extensive web of complex clock tree architecture for effective functionality. But with the increase in complexity, it is becoming more and more difficult to keep track about the clock signal effectively reaching to each intended sequential leaf cell. Clock signal, if gets blocked, can hamper the functionality of that particular IP and the effect, in essence, can further ripples down to broken functionality of the complete design. It is therefore imperative to thoroughly check the design for the locations where clock signal is unavailable in early stages of design implementations. This paper provides an algorithm in form of prototype debugger tool which aims at identifying the root cause of no clock signal reaching the clock pin of sequential cell in single iteration. It moves a step further by looking ahead and detecting all the possible potential blocking reasons, apart from the actual ones within a given clock path to a sequential cell in the same iteration. Experimental results on set top box chip show the effectiveness and the efficiency of this method by capturing all the actual and additional probable clock blocking reasons in a single step.