Dissipated energy of a low-power adiabatic CPAL JK-FF design using four-phase AC-clocked power supply based on 180 nm CMOS technology with various load capacitances

AC-clocked power supply is a well-established circuit philosophy based on switching the power supply. Energy efficiency has become a design concern in high performance devices. The energy harvesting is playing an increasingly important role in supplying energy to devices, circuits and systems. The process captures very small amounts of energy from one or more energy sources and accumulating them and storing them for later use. On the other side, there is a strong effort on the minimization of energy dissipation associated to the analog and digital circuitry. Therefore, the strategy of AC-clocked power supply follows this tendency. This paper presents a JK flip-flop using four-phase AC-clocked power supply. The analysis fall into one of the parameters which directly influence the energy dissipation: the output node load capacitance.