Circuit-level ESD protection simulation using behavior models in 28nm CMOS

Lack of accurate ESD device models and CAD methods makes on-chip ESD protection circuit design optimization and verification impossible. This paper reports a new circuit-level ESD protection simulation method using ESD behavior models to quantitatively analyze the ESD discharging functions at chip level, including checking the transient node voltage and branch current on a chip during ESD events. The new ESD circuit simulation method is validated using ICs designed and fabricated in 28nm CMOS.