Fast WLR assessment pulsed test optimizations for decisive DOE analysis base on correlation studies with extensive reliability characterization

In view of reducing the process development cycle times with plausible time-to-market goals, it is of great demands to speed up the assessment pace, but at the same time not to jeopardize for the high level of quality requirements. Highly robust designs and process margins are the key differentiators and should be enforced in particular for the automotive markets. In this work, development of the fast wafer-level reliability (FWLR) `pulsed' tests that are performed in a relatively short time span under highly accelerated stress conditions on the standard parametric test station (PCM) is revealed here. This is incredibly useful and saving a lot of time especially for compact DOE analysis. Few examples of evaluation studies on complicated process splits, as well as comprehensive layout variants will be demonstrated in this study with their effectiveness. Methodology on how the optimum stress test conditions at elevated temperatures with reasonable failing time test cycles will be discussed. They are determined and realized in correlation with the model fits from extensive reliability characterizations. Repeated test cycles with constant voltage stress up to certain plausible level as well as short ramping voltages are used respectively under specific circumstances, and in this way, the corresponding TDDB DC lifetimes can be deduced from such fast measurements. Decisive direction can be taken from such swift analysis. Such supportive fast measurements not only applicable in development phase, but also beneficial for monitoring high volume production stage so as to catch the problems in a much fast manner and reliable process can be guaranteed.