Efficient 2–16 GHz flat-gain stacked distributed power amplifier in 0.13μm CMOS using uniform distributed topology

This work presents the design and implementation of a flat-gain, efficient and wideband stacked distributed power amplifier (SDPA) in 0.13um CMOS technology. To obtain high output swing along with a reasonable gain, a four-transistor stack is utilized in four sections. Voltage alignment at the drain of each device in the stack is obtained by allowing a small AC swing at the gate due to voltage division between gate-source capacitance, Cgs and the external gate capacitor. Interstage matching is performed through peaking inductors. Further, the uniform distributed amplifier topology is adopted to control the impedance at each current injecting node from the stack to the artificial drain lines resulting into flat gain. Measured results show at least 10 ± 0.3dB small-signal gain from 2 -16 GHz. The SDPA demonstrated a saturated output power of 18 dBm with peak efficiency of 17% and an OIP3 of 22 dBm occupying an area of 0.83 mm
²
.