An FPGA hardware implementation approach for a phylogenetic tree reconstruction algorithm with incremental tree optimization

In this paper, we present an FPGA hardware implementation approach for a phylogenetic tree reconstruction with maximum parsimony algorithm. The algorithm, based on stochastic local search, uses the Indirect Calculation of Tree Lengths and the Incremental Tree Optimization methods. We evaluate and compare our new approach against previous hardware approaches, and against TNT, the fastest available parsimony program. We make this comparison for eight real-world biological datasets. We obtain acceleration rates per tree between 2.60 and 4.68 against a previous approach that does not use incremental optimization; between 2.19 and 4.05 against a previous approach that uses an alternative second-pass optimization; and, between 2.66 and 31.94 against TNT. Our approach is not only faster, but it does not use additional memories during the incremental optimization, as it is the case for a software approach.