128 Bit unsigned multiplier design and implementation using an efficient SQRT-CSLA

In Digital systems like digital signal processors, FIR filters and micro processors etc, Multiplier is one of the main hardware blocks. Generally, the performance of system is determined by the multiplier performance because the multiplier is generally the slowest element in the whole system and also it is occupying more area. In the multiplier, we use adder circuit repeatedly. So, an efficient adder circuit will be used in multipliers, it gives better performance. In the proposed work placing the new Carry Select Adders (CSLA) to enhance the multiplier performance. Carry Select Adder (CSLA) provides better performance with respect to speed and area. Previously a binary to excess one converter (BEC) based Square Root Carry Select Adder is designed but in that data dependency is very high, it gives some speed penalty. An efficient CSLA design is obtained using improved logic units to eradicate the data dependency and redundant logic operations. In this proposed work, the intended efficient Square Root Carry Select Adder is compared with BEC based CSLA of respective architectures, after having comparison the proposed CSLA is efficient with respective to area and delay is used in Multiplier design. This work gives better results regarding to the performance parameters such as delay and area of designed multiplier using new efficient square root carry select adder compared to BEC based CSLA multiplier.