Dynamic Choke Sensing for Timing Error Resilience in NTC Systems

Process variation (PV) is a conspicuous predicament for submicrometer VLSI circuits. In this paper, we illustrate “choke points” as a vital consequence of PV in the near-threshold computing domain. Choke points are PV affected sensitized logic gates with increased delay deviation. They dominate the choice of critical paths postfabrication. To mitigate the timing errors induced thereby, we propose dynamic choke sensing (DCS). This technique senses the timing error causing opcode sequences, and uses the knowledge to prevent similar sequences from causing errors in the future. We propose two variants of our scheme. Our techniques provide ~55% improvement in performance and ~73% improvement in energy efficiency as compared with popular timing error mitigation scheme, Razor, with minimal area and power overheads.