Ultra high density 3D SRAM cell design in Stacked Horizontal Nanowire (SN3D) fabric

CMOS scaling faces numerous challenges, among which device scaling, interconnect bottleneck, high leakage power and manufacturability are major ones. The scaling challenge is particularly acute for SRAM since maximum performance/power at highest density is required with every new generation. 3-D integration provides possible pathways to overcome the impediments faced in achieving ultra-high density SRAM. However 3-D integration techniques like monolithic 3-D, die-die [6-11][14-18], etc., show limited benefits and add additional constraints. Stacked Horizontal Nanowire-based 3-D CMOS (called SN3D hereafter)[19][20] is a true fine-grained 3-D IC fabric that can solve CMOS scaling challenges while providing significantly higher density, routability, performance/power advantages. Central to our approach is the formation of the device and routing structures onto stacked horizontal nanowires, and design and placement of symmetric CMOS circuits in 3-D. In this paper, we show design and analysis of SRAM circuit in SN3D and benchmark its potentials. We detail circuit design and implementation procedures considering underlying physical fabric. We analyze SRAM performance metrics: read, write, hold stability and performance margins, and compare the results with 2-D CMOS and Monolithic 3-D. Our simulation results showed 3.1x density, and 6.4x performance/watts benefits with respect to 2-D CMOS and 2.1 density and 5.7x performance/watts benefits over monolithic 3-D at 16nm. We have also achieved 1.7x Hold Margin (HM), 4.3x Read Margin (RM) and 1.2x Write Margin improvements over 2-D CMOS and monolithic designs.