A compact 14-bit 110 KS/s two-stage incremental ΣΔ ADC for CMOS image sensors

The requirements for data conversion in CMOS Image Sensors are increasing due to number and size of pixels and can not be met anymore by classic ramp converters. To address this issue, this paper presents a compact 14-bit two-stage Incremental-ΣΔ column-parallel ADC for use in CMOS Image Sensors. The ADC as well as a test array for a pixel matrix has been fabricated in a 110nm optical CMOS process with a 3.3V supply. The first ADC stage is 5 bit Incremental-ΣΔ, while the second stage is realized by reusing all circuit elements in a cyclic ADC configuration. This way the ADC column occupies an area of only 0.0029 mm
²
and is layout with a fine pitch of 9.6 μm. At a speed of 110 KS/s it consumes 123 μW and achieves a DNL and INL of +0.65/-0.83 LSB and +0.9/-0.81 LSB respectively.