A fully integrated charge pump using parasitics to increase the usable capacitance by 25 % and the efficiency by up to 18 % with poly-poly capacitors

In this paper, an advanced layout scheme of an integrated capacitor is presented which improves the efficiency of a poly-poly capacitor based voltage doubler charge pump. The main losses in voltage doubler charge pumps are mathematically described and the importance of low stray capacitances are discussed. By means of the improved poly-poly capacitor layout, the usable capacitance is increased while the stray capacitance is reduced. To quantify the improvements, a standard charge pump architecture is fabricated in a 0.35 μm CMOS technology with three different capacitor types. The presented measurement results show an efficiency of up to 77.9 % and an improvement by up to 18 % if compared to the same charge pump architecture using a standard capacitor. While following all design rules, the improved poly-poly capacitor layout scheme achieves almost the efficiency of a double metal-metal capacitor which allows typically for the highest efficiency of fully integrated charge pumps.