Local NOR and global NAND match-line architecture for high performance CAM

Locally NOR and globally NAND match-line architecture and sensing circuits applicable to the high performance content addressable memory(CAM) is proposed in this paper. As word-length of CAM gets longer, the capacitance of match-line gets larger and it causes performance degradation and large dynamic power consumption. Local match-lines are segments of large capacitive match-line and designed as NOR-type maximizing search speed. The results of local match-lines are gathered into NAND global match-line indicating the final evaluation result. Current limiting and clamping scheme is implemented to local match-line to reduce dynamic power by saturating voltage level after sufficiently developed. NAND global match-line reduces average power consumption by rarely switching its value. Replica match-line is implemented for asserting the evaluation of local match-line ends and enabling global match-line. With the proposed NOR local match-line and NAND global match-line sensing scheme, search time is achieved 0.61ns which is enhanced 73.7% and average power consumption is also slightly reduced compared to the conventional.