A buck converter with optimized dynamic response using lag-lead active voltage positioning

This paper proposes a lag-lead Active Voltage Positioning (AVP) technique that can be used in buck converters to minimize their output voltage transients during dynamic events, such as load pulses. The proposed technique is based on optimizing the output impedance of the converter across a wide range of frequencies, and therefore, output voltage transients in response to both narrow and wide load pulses can be minimized without increasing the converter's main control loop bandwidth or the output capacitance. The proposed technique is verified with a 5-MHz buck converter design in 0.18-μm CMOS, where compared to conventional lag-only AVP designs, over 70% and 60% reduction in output voltage transients are achieved for wide and narrow load pulses respectively.