A 50–66-GHz Phase-Domain Digital Frequency Synthesizer With Low Phase Noise and Low Fractional Spurs

Digital phase-locked loop (DPLL) frequency synthesizers have become popular for wireless applications in the sub-10-GHz range. However, mm-wave synthesizers still rely on analog PLLs, predominantly of the sub-harmonic, integerN-type. This paper describes the design and implementation of a 50-66-GHz phase-domain DPLL that uses a fundamental frequency capacitively degenerated digitally controlled oscillator (DCO) with 40-kHz frequency step. Following frequency division with a modulus of only 4, a two-step 8-bit time-todigital converter (TDC) digitizes the phase of the 12.5-16.5-GHz divider output with 450-fs resolution. Digital calibration based on the statistical element selection technique augmented by mean adaptation is used to mitigate TDC nonlinearity that results from random mismatches. Additional digital calibration techniques are introduced to mitigate DCO non-linearity and phase mismatches in the digital phase extraction sub-system, and to ensure robust operation of the inductor-less 4× frequency divider over process, voltage and temperature (PVT) variations. A 65-nm CMOS prototype of the DPLL occupies 0.45 mm
²
excluding pads and consumes 46 mA from a 1-V supply. The PLL achieves best (worst) case rms jitter of 220 (302) fs, best (worst) phase noise of -83/-94.5/-122 (-79/-88/ -116) dBc/Hz at 0.1/1/10 MHz offset, and -52.2(-48.3) dBc fractional spur.