Optimum scaling of stages in a frequency divider chain for best jitter FoM

This paper presents a method to determine the scaling factor for different stages in a divider chain(ripple counter) to get the best jitter FoM(minimum jitter times power) with a given divider configuration. An analytic expression for the FoM normalized to the first stage of the divider chain is derived and then optmized to get the best jitter FoM. The analysis shows that scaling down the divider stages in proportion to their input frequency results in a very high jitter and a very poor jitter FoM. For a cascade of divide-by-M stages, each stage should be scaled up by √M compared to the previous stage. Circuit simulation results confirming the analysis are given. When optimally sized, the FoM of a cascade of 8 divide-by-two stages is 14.7 dB better than scaling down the stages successively by a factor of two in order to lower the power dissipation in the low frequency stages. Compared to using 8 identical divide-by-two stages, optimal scaling has a 1.9 dB better FoM.