A switched-capacitor dendritic arbor for low-power neuromorphic applications

Power efficiency of the dendritic arbor has a high impact on the overall power efficiency of a neuromorphic design. We deploy a sub-threshold switched-capacitor mechanism and power gating to carry out summation of post synaptic potentials (PSPs) as well as capturing passive properties of dendrites through sampling PSPs on the capacitors and serializing them to perform summation rather than providing current through active devices as used in earlier designs. The power efficiency of the proposed 45nm CMOS circuit is demonstrated and compared to existing circuits used as dendritic arbors.