An efficient parallel resampling structure based on iterated short convolution algorithm

Due to adoption of a large amount of multipliers, the standard Farrow filter structure in digital resampling design has been the performance bottleneck of wideband signal demodulation. To improve demodulation performance, this paper proposes a full parallel resampling filter structure based on iterated short convolution algorithm (ISCA). The proposed design can effectively reduce the consumption of multipliers, by appropriately adding adders and delay elements. We implement the proposed design in a FPGA chip and test it by using a signal stream at a rate of 1.44 Giga-symbols per second (Gbps) under a four-parallel structure. The experimental results show that the consumption of multipliers and delay elements can be significantly reduced by about 36.8% and 57.2%, respectively, compared with conventional structure.