A 12-bit 40-MS/s calibration-free SAR ADC

This paper presents a new circuit technique named as “residue oversampling,” which is suitable for high-resolution analog-to-digital converters (ADCs). By adopting this technique and simplifying dynamic element matching (DEM), the impacts of capacitor mismatch and noise upon the successive-approximation register (SAR) ADCs are diminished significantly without calibrations. The proof-of-concept prototype was fabricated in a TSMC 40-nm CMOS technology. At 40-MS/s and 10-MS/s sampling rates, the measured peak signal-to-noise-and-distortion ratios (SNDRs) are 66.84 dB and 69.78 dB, respectively.