Local memory and logic arrangement for ultra-low power array processors

Array processors, and vision chips in particular, have mostly been designed from maximum processing speed point of view. There are applications in e.g. surveillance field, where the image content is analyzed rather rarely and where on the other hand the power consumption is of greater importance due to battery operation functionality. In sensing applications it is customary to use a coarser sensing for triggering a finer tuned sensor, where the coarse sensor is optimized for lower power and where the sensing abilities have been relaxed to that of a triggering ability. In this paper we continue on reporting on the progress of PMOS only based cellular array processor by introducing a possible arrangement for local binary memory and local binary logic.