An efficient VLSI architecture for iterative logarithmic multiplier

Logarithmic Number System (LNS) based multiplier plays a significant role in the fields of Digital Signal Processing (DSP), Image processing and Neural network which needs a lot of arithmetic operation. In all arithmetic operations, the multiplication is most hardware consuming component. Here, we give a possible solution to that problem by using an efficient VLSI architecture of Mitchell's algorithm based iterative logarithmic multiplier with seamless pipelined technique. The proposed work is based on the hardware minimization at the same error cost than of previously reported architectures. We use VHDL to design the existing and proposed Mitchell's algorithm based iterative logarithmic multiplier. Both multipliers design are evaluated with the Synopsys design compiler by using 90 nm CMOS technology and compared the results in terms of Data Arrival Time (DAT), Area, Power, Area Delay Product (ADP), and EPS (Energy per Sample). The proposed design involves 30.99 %, 31.10 %, and 20.84 % ADP, 5.12 %, 15.48%, and 23.55 % less EPS in comparisons of existing Mitchell's algorithm based iterative logarithmic multiplier for 8 bit, 16 bit, and 32 bit operations respectively.