Analysis and Visualization of Product Memory Layout in IP-XACT

Modern ASIC and FPGA based embedded products use model based design, in which both hardware and software are developed in parallel. Previously HW was completed first and the information handed over to SW team, typically in the form of register tables. The information was even manually copied to SW code, making any changes error-prone and laborious. IP-XACT is the most feasible standard to model HW also for the SW needs. The HW design connectivity and overall memory layout may change due to component instantiations, configurations and conditional operation states, which makes it difficult to create register tables even for documentation. Current register design tools fall short in serving the needs of both the HW and SW designer. All of them rely on low-level IP-XACT XML description that leaves much of the interpretation responsibility to the user, and most do not have any user-friendly visualization of the whole. Our approach is to perform a design connectivity analysis through hierarchies and configurations, analyze the memory structure based on it, and finally provide a novel, interactive visualization of system-wide memory maps. Our new Memory Designer for Kactus2 serves the hardware design by accessing and adjusting the memory layout from a single view disclosing end-to-end paths between masters and slaves. For SW development the Memory Designer shows the "programmer's view" to the system by hiding intermediate address translations and other connectivity related issues. As far as we know, this is the first visual, user-friendly memory tool for model based embedded system design.