A 1.4-mW 10-Bit 150-MS/s SAR ADC With Nonbinary Split Capacitive DAC in 65-nm CMOS

This brief presents a high-speed successive approximation register analog-to-digital converter (ADC) with nonbinary searching technique. By inserting redundancy in the first five decision steps, the digital-to-analog converter (DAC) settling errors can be tolerated and settling time can thus be reduced. In addition, split capacitor technology has also been adopted to further boost the conversion speed. With split switching method, no common mode voltage is needed in DAC reset phase and dynamic offset can be removed as well. Full adder-based encoder is employed to convert the raw 11-bit to 10-bit binary codes, showing less power penalty. The prototype ADC fabricated in 65-nm CMOS achieves 51.1 dB SNDR and 62.3 dB SFDR at 150-MS/s sampling rate. It consumes 1.4 mW, resulting in a Walden figure of merit of 31.8 fJ/conversion step.