Etching process development for 3D wafer level via last TSV package

Via last TSV (through silicon via) technology is more and more applied in 3D WLCSP, which can decrease package volume and increase I/O density. The process of via last includes temporary bonding, grinding, photolithograph, silicon etching, SiO
₂
etching, CVD, PVD, plating and so on. Silicon etching and SiO
₂
etching are important process of via last TSV package for interconnect technology. Temporary bonding and grinding will affect TTV of silicon wafer, which can cause “notch” and “footing” in etching process. This paper presents a typical process of via last TSV package. The front pillar will choose Cu/Ni/Au, and thickness is 10um/3um/0.05um for flip chip package with other dies. The backside pillar can be Cu/Ni/SnAg. The thickness of silicon wafer will attain 100um, and CD of via can be 35um. The result of O/S test can be 99%. The reaction time ratio of SF
₆
and C
₄
F
₈
is 2.5:1. The etching flow of SF
₆
is 300sccm, and the passivation flow C
₄
F
₈
of is 180sccm. The scallop can be about 50nm. Higher bias ratio frequency can increase CD of via. 10% duty cycle can improve notch phenomenon. A metrology for thickness of SiO
₂
at the bottom of vertical via is used online, which can help to decrease open risk of SiO
₂
residual.