High-level path activation technique to speed up sequential circuit test generation

In current paper, a novel high-level symbolic path activation technique for sequential circuit test generation is proposed. The technique has been implemented as a part of a hierarchical ATPG tool which utilizes internal representation of multi-level (register-transfer and structural levels) decision diagram models. Experiments show that the proposed method allows to reach high fault coverages for circuits with complex sequential structures in a very short time.