Modeling and parameter extraction of BJT substrate resistance

This paper presents an efficient method to account for the layout dependent substrate resistance for bipolar transistors. The method enables a single set of parameters to fit for all the identical transistors with different substrate resistance, thereby allowing circuit designers to layout the substrate contact differently for each transistor. This method is especially beneficial to the circuit layout optimization where both the die size and the effective noise shielding for the critical transistor must be considered. The method is based on the fast calculation algorithm developed by Gharpurey (1996) for the modeling of substrate noise coupling. To verify the methodology for RF applications, a direct method is used to extract the substrate resistance from measured S-parameters. The experimental results show that the algorithm used to calculate the substrate resistance is accurate and can improve the accuracy of simulated Y/sub 22/ up to 5 GHz.